Documento de conferencia

Efficient VHDL implementation of an upscaling function for real time video applications

Conference Proceeding cp
Proceedings - IEEE International Symposium on Circuits and Systems
  • Volumen: 2019-May
  • Fecha: 01 enero 2019
  • ISSN: 02714310
  • ISBN: 9781728103976
  • Tipo de fuente: Ponencia
  • DOI: 10.1109/ISCAS.2019.8702453
  • Tipo de documento: Documento de conferencia
  • Editorial: Institute of Electrical and Electronics Engineers Inc.
© 2019 IEEEThis paper describes the design and the implementation of a high-performance area-efficient upscaling function on a FPGA. The proposed function performs the resizing of real time video images, from M x N pixels to 2M x 2N pixels, using a bilinear interpolation method. The hardware implementation has been carried out using an RTL structural description in VHDL, to maximize the use of the specific resources of the FPGA, especially its memory resources (BRAM). For this purpose, an optimized memory access schema, that allows the best performance of the architecture with the least use of hardware resources, is proposed. Details of the design and the implementation on a Zynq UltraScale+ MPSoC are given, as well as speed-performance and area utilization. The proposed solution significantly improves the results achieved using this schema compared with those obtained using the Resize function from the Xilinx OpenCV library, when both are configured to obtain the same spatial transformation.

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