Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm
Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
- Fecha: 01 enero 2014
- ISBN: 9783000446450
- Tipo de fuente: Ponencia
- DOI: 10.1109/FPL.2014.6927409
- Tipo de documento: Documento de conferencia
- Editorial: Institute of Electrical and Electronics Engineers Inc.
© 2014 Technical University of Munich (TUM).This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15×15 pixels. This process comprises several steps, including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 ¿s and 8.74 ¿s for a 100 MHz FPGA).