Documento de conferencia

Evaluation of VHDL-AMS models of a high performance ADC

Conference Proceeding cp
IEEE International Symposium on Industrial Electronics
  • Fecha: 01 diciembre 2007
  • Páginas: 1424-1429
  • ISBN: 1424407559
  • Tipo de fuente: Ponencia
  • DOI: 10.1109/ISIE.2007.4374810
  • Tipo de documento: Documento de conferencia
High performance analog to digital converters are a key element for the development of high resolution image sensors. Engineers are continuously developing faster, more resolution, and less power dissipation converters suitable to be used in high resolution television cameras or portable image processing devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital techniques and the analog expertise knowledge. However, in such circuits the analog part represents only a small portion of the total die, but it is a bottleneck which dominates the total design time. To reduce the simulation time it becomes necessary the use of high level models with a good trade off between accuracy and simulation speed. In this paper performance of two different VHDL-AMS high level models of a pipeline ADC are compared. Both approaches are evaluated versus a SPICE model of the real pipeline ADC. ©2007 IEEE.

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