Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
Electronics Letters
- Volumen: 36
- Número: 20
- Fecha: 28 septiembre 2000
- Páginas: 1680-1682
- ISSN: 00135194
- Tipo de fuente: Revista
- DOI: 10.1049/el:20001202
- Tipo de documento: Artículo
- Editorial: IEEStevenage, United Kingdom
A technique of translating high-level analogue dynamic system behavioural models from VHDL-AMS parse trees into circuit-level netlists is described. The primary application of this work is automatic synthesis of general analogue dynamic systems with feedback. The technique is demonstrated with a practical example of Lorenz's chaos system synthesis.