Neural parallel-hierarchical-matching scheduler for input-buffered packet switches

  • F. J. González-Castaño /
  • C. López-Bravo /
  • R. Asorey-Cacheda /
  • J. M. Pousada-Carballo /
  • P. S. Rodríguez-Hernández
Journal ar
IEEE Communications Letters
  • Volumen: 6
  • Número: 5
  • Fecha: 01 mayo 2002
  • Páginas: 220-222
  • ISSN: 10897798
  • Tipo de fuente: Revista
  • DOI: 10.1109/4234.1001670
  • Tipo de documento: Artículo
Input-buffered packet switches boosted with high-performance schedulers achieve near-100% throughput. Several authors have proposed the use of neural schedulers. These schedulers have a fast theoretical convergence, but the standard deviation of the number of iterations required can be arbitrarily large. In a previous paper, the authors proposed a hybrid digital-neural scheduler, HBRTNS, with bounded response time: O(N) clock steps. As an evolution of that concept, the authors present a two-stage neural Parallel-Hierarchical-Matching scheduler (nPHM), which generates high quality solutions in few clock steps. We present numerical comparisons with diverse state-of-the-art algorithms and the ideal output-buffered case.

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