Conference Paper

Simulation-based low-level optimization tool for analog integrated circuits

Conference Proceeding cp
Proceedings of SPIE - The International Society for Optical Engineering
  • Volumen: 5837 PART II
  • Fecha: 09 December 2005
  • Páginas: 685-692
  • ISSN: 0277786X
  • Source Type: Conference Proceeding
  • DOI: 10.1117/12.608724
  • Document Type: Conference Paper
In this paper, a tool based on free software to perform low level optimization on analog designs is presented. Nowadays, the use of design automation tools for microelectronic circuits design is extending from digital to analog circuits, due in part to the fact that although the analog part of a mixed signal ASIC takes only the 10% of the silicon area, it represents almost 90% of the whole design time. For analog circuits, design process can be divided in two major tasks: topology selection and device sizing. The tool here presented consists on a simulation based optimizer, which is used to perform automatic low level analog circuit sizing. The tool is composed of three modules: a layout generator, which includes a parasitic extractor, an analog circuit simulator and a circuit optimizer. The two first modules are respectively Magic and Spice from Berkeley, while the third one, the optimizer, has been developed to evaluate dc, ac, and transient sensitivity simulations performed by Spice and make corrections on the layout sizing. Optimization process starts with a certain topology and standard sized devices, which is then extracted by Magic and simulated by Spice. Performance is evaluated and a sizing correction is proposed. These simulations and corrections are done on an iterative loop until circuit performance reaches design parameters. The tool is demonstrated with an example of a simple analog subcircuit optimization, where parameters like silicon area or power dissipation are optimized, while the circuit keeps on design parameters.

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